Flash memories have been focused in researches for non-volatile memory devices due to their advantages such as convenience to use, high storage density, and excellent reliability. Since the debut of the first flash memory in 1980s, flash memories have been widely used in cell phones, laptop computers, palm-sized computers, USB flash disks and other portable and communication devices, accompanying with technological development and increasing needs for good storage devices for various electronic products. As a kind of persistent storage device, a flash memory stores information by changing threshold voltages of transistors or memory cells so as to switch on or off the gate electrode channels to prevent the stored information from being lost due to failure of power supply. Flash memories are a special variety of electrically erasable programmable read-only memory devices, which currently take a dominant share and grow fastest in the market of non-volatile semiconductor memory devices.
Whereas, due to the limitation in programming voltage, it is a great challenge to increase the existing storage density of flash memories by size shrinkage. Therefore, developing a flash memory with a high storage density is currently an important motivation for technological development in this field. However, in this regard, limited by the structure of conventional flash memories, reducing the programming voltage, which is required for increasing the storage density, is difficult to achieve. In general, a flash memory device includes a split-gate structure, a stacked-gate structure, or a combination of the above two. When comparing the two structures, the split-gate structure has advantages in both programming and erasing performance because of a special configuration. And it has a higher programming efficiency, an advanced word-line arrangement which can avoid the “over-erasure” and other advantages. For these reasons, split-gate structures have wider applications. On the other hand, as a split-gate structure adopts an additional word line than a stacked-gate structure, it generally leads to a greater chip size. This is unfavorable for producing a semiconductor memory device with densely packed memory cells and thus a high storage intensity which encourages the storage circuit layout to be designed as small as practicable. Therefore, in order to enable memory cells to be packed in a high density, there is a need for improving the structure of the existing semiconductor memory device.
In addition, as each hit in memory arrays connects to a contact metal wire, rather densely arranged metal wires are typically formed in wafer in the manufacturing of the semiconductor memory device. Increasing the density of memory cells further raises the density of the metal wires and thus adds manufacturing difficulties because it requires extremely fine lines to be formed in relevant masking and etching processes. Therefore, the method of increasing memory cell density by forming more memory cells in the wafer imposes critical requirements on manufacturing processes, which limits its applications.